A one-time programmable read-only memory (OTPROM) array is a memory architecture that includes a plurality of memory cells that can each be programmed a single time. Each memory cell can store the equivalent of one bit (i.e., a logic high value or state, or a logic low value or state) and is commonly referred to as a bit cell. The terms memory cell and bit cell are used interchangeably herein.
Typically all memory cells of a OTPROM array are programmed during manufacturing such that all bits read a logical one (1). After manufacturing each memory cell of the OTPROM array can be programmed one time. To allow the memory cell to be programmed, each memory cell includes a fuse that can be “burned” to program the memory cell. Here, the term “burn” is used to refer to the process of programming a memory cell and more particularly to the process of “burning” a fuse of the memory cell to cause that memory cell to read a logical zero (0). Once a memory cell has been programmed, it is not possible to program it again since the fuse cannot be unburned.
In order to determine the current required to burn the fuses of the OTPROM array, one memory cell of the OTPROM array can be selected and tested. A current meter can be used to measure a programming current (Iprog) that can be used to program the memory cells of the OTPROM array.
FIG. 1 shows a programming path for a particular memory cell of an OTPROM array (not illustrated in FIG. 1) that is selected and used during testing to measure a programming current (Iprog) that can be used program the memory cells of the OTPROM array. FIG. 1 also illustrates a bit line driver 110 for the memory cell 150 and other external elements 170, 180 that are not part of the OTPROM array, but that are used during testing of the array to measure the programming current (Iprog) 172. As illustrated in FIG. 1, a programming voltage source (Vprog) 180 is coupled to the bit line driver 110 for memory cell 150. During testing, this particular memory cell 150 of the array can be selected so that it is coupled to a programming voltage source (Vprog) 180. Thus, the memory cell 150 is one memory cell of an OTPROM array that is selected during testing for measuring a programming current (Iprog) 172 via current meter 170. In this regard, it is noted that the memory cell 150 can be any memory cell in the OTPROM array, and that any other memory cell (not illustrated) of the OTPROM array could be selected and used to measure a programming current (Iprog) 172.
The memory cell includes an N-channel transistor 130 and fuse 120 having a resistance (Rpre). Each memory cell is coupled to a bit line 132 and a word line 134 that are used to select that memory cell 150. When the p-channel transistor 110 (that is used to implement the bit line driver) is turned on by applying an appropriate voltage at its gate and the N-channel transistor 130 of the memory cell 150 is turned on by applying an appropriate voltage at its gate, a programming current (Iprog) 172 is allowed to flow through node B and the memory cell 150 to ground 190. This programming current (Iprog) 172 can be measured via the current meter 170.
A problem with this arrangement is that the programming current (Iprog) 172 that flows through the fuse 120 and will eventually cause the fuse 120 to burn, which is undesirable since the memory cell 150 is no longer useful because it can no longer be programmed. It would be desirable to provide a solution that avoids burning of the fuse 120 during measurement of the programming current (Iprog) 172.
One approach for preventing the fuse 120 from burning is to use a fuse array. FIG. 2 illustrates a conventional fuse array 200 that can replace the fuse 120 of FIG. 1. The fuse array 200 is a 10×10 array of the fuses 120-1 . . . 120-100. The values of the fuses 120-1 . . . 120-100 are selected such that the fuse array 200 has the same resistance value (Rpre) as the fuse 120 of FIG. 1. The fuse array 200 provides one possible solution to the problem of unwanted burning because as the programming current (Iprog) 172 flows through the array 200 it splits over ten different paths. As such, only 1/10th of the programming current (Iprog) 172 flows through each of the fuses 120-1 . . . 120-100 and the fuses 120-1 . . . 120-100 do not burn. However, this approach is has drawbacks.
For example, employing 100 fuses 120-1 . . . 120-100 instead of one fuse 120 consumes a much larger area. Another problem is that the wiring to connect 100 fuses causes unwanted parasitic resistors that reduce measurement accuracy. This is particularly true when the fuses 120-1 . . . 120-100 each have low resistance values (e.g., 30 ohms) Although none of the fuses 120-1 . . . 120-100 burn when using this approach, it would be desirable to provide an alternative approach to the one illustrated in FIG. 2 that does not suffer from the drawbacks mentioned above, and is not prone to measurement errors (e.g., reduced measurement accuracy particularly in case of metal fuses with low Rpre values (e.g. 30 ohms))
Another approach for preventing the fuse 120 from burning is to replace the fuse 120 with a variable resistor having a resistance value that is close to the measured resistance value (Rpre) of the fuse 120. However, this approach can be difficult to implement since the accuracy of the variable resistor is difficult to control due to process variations, non-linearities, temperature effects, etc. Differences between the resistance value of the variable resistor and the resistance value (Rpre) of the fuse 120 can result in additional errors when measuring the programming current (Iprog) 172.
Accordingly, it is desirable to provide improved techniques and technologies that can be used to measure a programming current for programming a memory cell of a one-time programmable read-only memory array without causing unwanted burning of the fuse associated with the selected memory cell. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description of the invention and the appended claims, taken in conjunction with the accompanying drawings and this background of the invention
The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.